Z85C3010PSG

Product Summary

The Z80C30/Z85C30 Serial Communications Controller (SCC), is a pin and software compatible CMOS member of the SCC family introduced by Zilog? in 1981. It is a dual channel, multi-protocol data communications peripheral that easily interfaces with CPU’s with either multiplexed or non-multiplexed address/data buses. The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allow the SCC to be configured to various serial communications applications. Figure 1 displays a block diagram of the SCC. The many on-chip features such as Baud Rate Generators (BRG), Digital Phase Locked Loops (DPLL), and crystal oscillators reduce the need for an external logic. Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support high speed SDLC transfers using DMA controllers.

Parametrics

Specifications of Z85C3010PSG
Processor Type Z80 Features Error Detection and Multiprotocol Support
Speed 10MHz Voltage 5V
Mounting Type Through Hole Package / Case 40-DIP (0.620", 15.75mm)
Cpu Speed 8MHz Digital Ic Case Style DIP
No. Of Pins 40 Supply Voltage Range 5V
Operating Temperature Range 0?°C To +70?°C Svhc No SVHC (18-Jun-2010)
Base Number 85 Rohs Compliant Yes
Clock Frequency 10MHz Lead Free Status / RoHS Status Lead free / RoHS Compliant
Other names 269-3934
Z85C3010PSG  

Features

Z85C30 — Optimized for Non-Multiplexed Bus Microprocessors. ? Z80C30 — Optimized for Multiplexed Bus Microprocessors. ? Pin Compatible to NMOS Versions. ? Two Independent, 0 to 4.1 Mbit/Second, Full-Duplex Channels. Each channel with Separate Crystal Oscillator, Baud Rate Generator (BRG), and Digital Phase-Locked Loop (DPLL) for Clock Recovery. ? Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or FM Data Encoding. ? Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits Per Character, Programmable Clock Factor, Break Detection and Generation; Parity, Overrun, and Framing Error Detection. ? Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 or CRC-CCITT Preset to either 1s or 0s. ? SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, and SDLC Loop. ? Software Interrupt Acknowledge Feature (not available with NMOS). ? Local Loopback and Auto Echo Modes. ? Supports T1 Digital Trunk. ? Enhanced DMA Support (not available with NMOS) 10 x 19-Bit Status FIFO 14-Bit Byte Counter. ? Speeds: – Z85C3O — 8.5, 10, 16.384 MHz – Z80C3O — 8, 10 MHz

Diagrams